VLSI Design and Embedded Systems

VLSI Design and Embedded SystemsCHAPTER 1INTRODUCTION1.1 MotivationPhase locked loop (PLL) 1-3 is the heart of the m whatever modern electronics as rise as communication system. modernly plenty of the researches impart conducted on the origination of var. locked loop (PLL) lap and still research is going on this topic. or so of the researches have conducted to realize a higher lock escape PLL with lesser lock clock time 4 and have tolerable variant dissension. The close versatile use of the phase locked loops (PLL) is for clock generation and clock recovery in microprocessor, networking, communication systems, and absolute absolute oftenness synthesisers. Phase locked-loops (PLLs) ar commonly used to generate well-timed on-chip pin grass in high-per organizeance digital systems. Modern wireless communication systems employ Phase Locked Loop (PLL) mainly for synchronization, clock synthesis, skew and jitter reduction 5. Phase locked loops divulge wide application i n some(prenominal) modern applications mostly in advance communication and instrumentation systems. PLL being a mixed signal travel involves throw challenge at high frequency.Since its inspection in early 1930s, where it was used in the synchronization of the horizontal and vertical scans of television, it has come to an advanced resile of integrated rotary (IC). Today found uses in many other applications. The first PLL ICs were available around 1965 it was built using purely analog comp iodinnt. Recent advances in integrated circuit trope techniques have led to the development of high action PLL which has become more economical and reliable. presently a tout ensemble PLL circuit can be integrated as a part of a king-sizedr circuit on a single chip.There argon mainly five opposes in a PLL. These argon phase frequency detector (PFD), charge pump (CP), low pass loop filter (LPF), electromotive force affirmled oscillator (VCO) and frequency rail-splitter. Presently alm ost all communication and electronics devices operate at a higher frequency, so for that purpose we need a faster locking PLL. So on that point ar a lot of challenges in externalizeing the mentioned different blocks of the PLL to operate at a higher frequency. And these challenges motivated me towards this research topic. In this work mainly the faster locking of the PLL is concentrated by goodly choosing the circuit architectures and parameters. The optimization of the VCO circuit is as well as carried out in this work to attempt a split up frequency precision.1.2 Organization of ThesisBefore going into the details of the PLL, the motivation behind this work is mentioned in the Chapter 1 of the thesis. Chapter 2 shortly describes the whole PLL system. An introduction to the PLL circuit is mentioned in the section 2.1. Section 2.2 contains the detail architecture of the whole PLL system. Different types of PLLs atomic number 18 mentioned in the section 2.3. Section 2.4 exp lains the rudimentary terms used in the PLL system spell the consecutive sections give the details about the noise and application of the PLL.Chapter 3 builds the concepts of optimization. Definition of optimization technique and different circuit optimization techniques are presented in section 3.1 and 3.2 respectively. Section 3.3 gives the brief outline of the concept of geometric programming and gibbose optimization. The optimization of the CSVCO circuit is explained in section 3.4.The design and synthesis of the PLL is described in Chapter 4. The different design environments used in this work is mentioned in the section 4.1. The adopted design procedure is explained in section 4.2. Section 4.3 gives the design specifications and parameters of the work.The simulation results of the different circuits used in the PLL are depicted in the different sections of the Chapter 5. The performance of the CSVCO intentional using convex optimization is compared with that of the traditi onal method acting in section 5.3. Section 5.5 gives the different simulation results of the PLL and its performance comparison in the midst of schematic and contain layout aim. At last Chapter 6 provides the conclusion that inferred from the work.CHAPTER 2PHASE LOCKED LOOP2.1 IntroductionA PLL is a c stomachd-loop feed rear end system that sets fixed phase relationship mingled with its output clock phase and the phase of a persona clock. A PLL is capable of tracking the phase changes that falls in this bandwidth of the PLL. A PLL also multiplies a low-frequency credit clock CKref to produce a high-frequency clock CKout this is known as clock synthesis.A PLL has a negative feedback control system circuit. The main quarry of a PLL is to generate a signal in which the phase is the corresponding as the phase of a reference signal. This is achieved after many iterations of comparison of the reference and feedback signals. In this lock mode the phase of the reference and feedback signal is zero. After this, the PLL continues to compare the two signals but since they are in lock mode, the PLL output is constant.The raw material block diagram of the PLL is shown in the physique 2.1. In general a PLL consists of five main blocksPhase detector or Phase Frequency Detector (PD or PFD)Charge Pump (CP) funky Pass Filter (LPF)Voltage Controlled Oscillator (VCO)Divide by N CounterThe Phase frequency Detector (PFD) is one of the main parts in PLL circuits. It compares the phase and frequency difference between the reference clock and the feedback clock. Depending upon the phase and frequency deviation, it generates two output signals UP and dismantle. The Charge Pump (CP) circuit is used in the PLL to combine two(prenominal) the outputs of the PFD and give a single output. The output of the CP circuit is fed to a Low Pass Filter (LPF) to generate a DC control voltage. The phase and frequency of the Voltage Controlled Oscillator (VCO) output depends on the generat ed DC control voltage. If the PFD generates an UP signal, the geological fault voltage at the output of LPF increases which in turn increase the VCO output signal frequency. On the contrary, if a lot signal is generated, the VCO output signal frequency decreases. The output of the VCO is then fed back to the PFD in give to recalculate the phase difference, and then we can create closed loop frequency control system.2.2 PLL ArchitectureThe architecture of a charge-pump PLL is shown in visualise 2.2. A PLL comprises of several components. They are (1) phase or phase frequency detector, (2) charge pump, (3) loop filter, (4) voltage-controlled oscillator, and (5) frequency divider. The croping of each block is briefly explained below.2.2.1 Phase Frequency DetectorThe Phase frequency Detector (PFD) is one of the main part in PLL circuits. It compares the phase and frequency difference between the reference clock and the feedback clock. Depending upon the phase and frequency deviatio n, it generates two output signals UP and DOWN. Figure 2.3 shows a traditional PFD circuit.If there is a phase difference between the two signals, it will generate UP or DOWN synchronized signals. When the reference clock rising advance leads the feedback stimulus clock rising boundary line UP signal goes high while keeping DOWN signal low. On the other hand if the feedback input clock rising edge leads the reference clock rising edge DOWN signal goes high and UP signal goes low. Fast phase and frequency acquisition PFDs 6-7 are generally preferred over traditional PFD.2.2.2 Charge Pump and Loop FilterCharge pump circuit is an important block of the whole PLL system. It converts the phase or frequency difference information into a voltage, used to tune the VCO. Charge pump circuit is used to combine both the outputs of the PFD and give a single output which is fed to the input of the filter. Charge pump circuit gives a constant watercourse of value IPDI which should be deadened to the supply voltage variation 8. The amplitude of the up-to-the-minute always remains same but the polarity changes which depend on the value of the UP and DOWN signal. The schematic diagram of the charge pump circuit with loop filter is shown in the Figure 2.4.When the UP signal goes high M2 transistor turns ON while M1 is OFF and the output electric current is IPDI with a positive polarity. When the down signal becomes high M1 transistor turns ON while M2 is OFF and the output current is IPDI with a negative polarity. The charge pump output current 3 is accustomed byIPDI=IPUMPIPUMP4=2IPUMP4=IPUMP2=KPDI (1)Where KPDI=IPUMP2 (amps/radian) (2)The passive low pass loop filter is used to convert back the charge pump current into the voltage. The filter should be as compact as possible 9.The output voltage of the loop filter controls the oscillation frequency of the VCO. The loop filter voltage will increase if Fref rising edge leads Fin rising edge and will decrease if Fin rising edge leads Fref rising edge. If the PLL is in locked state it maintains a constant value.The VCO input voltage is given byVinvco = KF IPDI (3)Where KF is the gain of the loop filter.2.2.3 Voltage Controlled OscillatorAn oscillator is an autonomous system which generates a periodic output without any input. The most popular type of the VCO circuit is the current starved voltage controlled oscillator (CSVCO). Here the number of inverter stages is fixed with 5. The simplified construe of a single stage current starved oscillator is shown in the Figure 2.5.Transistors M2 and M3 operate as an inverter while M1 and M4 operate as current sources. The current sources, Ml and M4, limit the current available to the inverter, M2 and M3 in other words, the inverter is starved for current. The desired center frequency of the knowing circuit is 1GHz with a supply of 1.8V. The CSVCO is designed both in usual manner as mentioned in 3, 10, 11. The general circuit diagram of the current starved v oltage controlled oscillator is shown in the Figure 2.6.To determine the design equations for the CSVCO, consider the simplified view of VCO in Figure 2.5. The extreme capacitance on the drains of M2 and M3 is given byCtot=52Cox(LpWp+LnWn) (4)The time it takes to charge Ctot from zero to VSP with the constant current ID4 is given byt1=VSPID4Ctot (5)While the time it takes to discharge Ctot from VDD to VSP is given byt1=VDD-VSPID1Ctot (6)If we set ID4= ID1=ID then the sum of t1 and t2 is given byt1+t2=VDDIDCtot (7)The oscillation frequency of CSVCO for N number of stage isfosc=1Nt1+t2=IDNCtotVDD (8)This is equal to fcenter when Vinvco=VDD2 (9)The gain of the VCO is given byKVCO=fmax-fminVmax-Vmin HzV (10)2.2.4 Frequency DividerThe output of the VCO is fed back to the input of PFD through the frequency divider circuit. The frequency divider in the PLL circuit forms a closed loop. It scales down the frequency of the VCO output signal. A simple D flip flop (DFF) acts as a frequency div ider circuit. The schematic of a simple DFF based divide by 2 frequency divider circuit is shown in the Figure 2.7.2.3 Types of PLLThere are mainly 4 types of PLL are available. They are. Liner PLLDigital PLLAll Digital PLLSoft PLL2.4 Terms in PLL2.4.1 Lock in RangeOnce the PLL is in lock state what is the range of frequencies for which it can keep itself locked is called as lock in range. This is also called as tracking range or holding range.2.4.2 Capture RangeWhen the PLL is initially non in lock, what frequency range can make PLL lock is called as capture range. This is also known as acquisition range. This is directly proportional to the LPF bandwidth. Reduction in the loop filter bandwidth thus improves the rejection of the out of band signals, but at the same time the capture range decreases, pull in time becomes larger and phase margin becomes poor.2.4.3 Pull in TimeThe total time taken by the PLL to capture the signal (or to establish the lock) is called as Pull in Time o f PLL. It is also called as Acquisition Time of PLL.2.4.4 Bandwidth of PLLBandwidth is the frequency at which the PLL begins to lose the lock with reference.2.5 Noises in PLLThe output of the working system deviates from the desired response. This is because of the imperfections and noises in the system. The supply noise also affects the output noise of the PLL system 12. There are mainly 4 types of noises. They are explained below.2.5.1 Phase NoiseThe phase fluctuation due to the random frequency variation of a signal is called as phase noise. This is mostly affected by oscillators frequency stability. The main sources of the phase noise in PLL are oscillator noise 12-15, PFD and frequency divider circuit. The main components of the phase noise are thermal and flicker noise.2.5.2 JitterA jitter is the short term-term variations of a signal with respect to its ideal position in time 16-19. This problem negatively impacts the information transmission quality. Jitter and phase noise are closely related and can be computed one from another 18. Deviation from the ideal position can slip away on either leading edge or trailing edge of signal. Jitter whitethorn be induced and coupled onto a clock signal from several different sources and is not uniform over all frequencies. Excessive jitter can increase bit error rate (BER) of communication signal 19. In digital system Jitter leads to violation in time margins, causing circuits to behave improperly.2.5.3 prickleNon-desired frequency content not related to the frequency of oscillation and its harmonics is called as Spur. There are mainly two types of spur. They are reference spur and fractional spur. reference book spur comes into picture in an integer PLL while fractional spur plays a major role in fractional PLL. When the PLL is in lock state the phase and frequency inputs to the PFD are essentially equal. There should not be any error output from the PFD. Since this can create problem, so the PFD is designed such that, in the locked state the current pulses from the CP will have a very narrow width as shown in the Figure 2.9. Because of this the input control voltage of the VCO is modulated by the reference signal and thus produces Reference Spur 20.2.5.4 Charge Pump Leakage CurrentWhen the CP output from the synthesizer is programmed to the high impedance state, in practice there should not be any current flow. But in practical some leakage current flows in the circuit and this is known as charge pump leakage current 20.2.6 Applications of PLLThe demand of the PLL circuit increases day by day because of its wide application in the area of electronics, communication and instrumentation. The recent applications of the PLL circuits are in memories, microprocessors, hard magnetized disc drive electronics, RF and wireless transceivers, clock recovery circuits on microcontroller boards and optical fiber receivers. Some of the PLL applications are mentioned below.1. Frequency SynthesisA fre quency synthesizer is an electronic system for generating a range of frequencies from a single fixed time base or oscillator.2. Clock GenerationMany electronic systems implicate processors of various sorts that operate at hundreds of megahertz. Typically, the clocks supplied to these processors come from clock generator PLLs, which multiply a rase-frequency reference clock (usually 50 or ascorbic acid MHz) up to the operating frequency of the processor. The multiplication particularor can be quite large in cases where the operating frequency is multiple GHz and the reference crystallization is just tens or hundreds of megahertz.3. Carrier Recovery (Clock Recovery)Some data spuds, especially high-speed serial data streams (such as the raw stream of data from the magnetic head of a disk drive), are sent without an accompanying clock. The receiver generates a clock from an approximate frequency reference, and then phase-aligns to the transitions in the data stream with a PLL. Thi s process is referred to as clock recovery.4. SkewReductionThis is one of the very popular and earliest uses of PLL. Suppose synchronous pair of data and clock lines enter a large digital chip. Since clock typically drives a large number of transistors and logic interconnects, it is first apply to large buffer. Thus, the clock distributed on chip may suffer from substantial skew with respect to data. This is an undesirable effect which reduces the timing budget for on-chip operations.5. Jitter and Noise ReductionOne desirable property of all PLLs is that the reference and feedback clock edges be brought into very close alignment. The average difference in time between the phases of the two signals when the PLL has achieved lock is called the static phase offset. The variance between these phases is called tracking jitter. Ideally, the static phase offset should be zero, and the tracking jitter should be as low as possible.CHAPTER 3CONVEX OPTIMIZATION OF VCO IN PLL3.1 What is an opt imization technique?optimization technique is nothing but the purpose of the action that optimises i.e. minimizes or maximizes the result of the objective function. Optimization technique is applied to the circuits aiming at run a risking out the optimized circuit design parameter to achieve either the best performance or the desired performance. Optimization techniques are a set of most powerful tools that are used in efficiently handling the design resources and there by achieve the best result. Mainly optimization techniques are applied to the circuit for the selection of the component values, devices sizes, and value of the voltage or current source.3.2 Types of circuit optimization methodThere are mainly four types of circuit optimization methods exist. They are absolute optimizationKnowledge based optimizationGlobal optimization methodConvex optimization and geometric programming3.2.1 Classical Optimization MethodsIn case of analog circuit CAD, unmingled optimization metho ds 21, such as steepest descent, sequential quadratic programming, and Lagrange multiplier methods are mainly used. These methods are used with more complicated circuit models, including even full SPICE simulations in each iteration. This method can palm a wide conversion of problem. For this there is a need of a set of performance measures and computation of one or more derivatives. The main disadvantage of the classical optimization methods is that the ball-shaped optimal solution is not possible. This method fails to regulate a feasible design even one exist. This method gives only the local minima instead of spheric solution. Since many different initial designs are considered to get the global optimization, the method becomes slower. Because of the human intervention (to give good initial designs), the method becomes less automated. The classical methods become slow if complex models are used.3.2.2 Knowledge-Based MethodsKnowledge-based and expert-systems methods such as genetic algorithm or evolution systems, systems based on Fuzzy logic, and heuristics-based systems have also been widely used in analog circuit CAD 21. In case of knowledge based methods, there are few limitations on the types of problems, specifications, and performance measures that are to be considered. These methods do not require the computation of the derivatives. This is not possible to find a global optimal design solution using these methods. The final design is decided on the basis of the initial design chosen and the algorithm parameters. The disadvantage of the knowledge based methods is that they simply fail to find a feasible solution even when one may exist. There is a need of human intervention during the design and the training process.3.2.3 Global Optimization MethodsGlobal optimization methods such as branch and bound and simulated annealing are also used in analog circuit design 21. These methods are guaranteed to find the global optimal design solution. The glob al optimal design is determined by the branch and bound methods unambiguously. In each iteration, a suboptimal feasible design and also a lower bound on the achievable performance is maintained by this method. This enables the algorithm to terminate non-heuristically, i.e., with complete trustfulness that the global design has been found within a given tolerance. The branch and bound method is extremely slow, with computation growing exponentially with problem size. The caparison in a locally optimal design can be avoided by using simulated annealing (SA). This method can compute the global optimal solution but not guaranteed. Since there is no real-time lower bound is available, so termination is heuristic. This method can also handle a wide variety of performance indices and objects. The main advantage of SA is that it handles the continuous variables and discrete variables problems efficiently and reduces the chances of getting a non-globally optimal design. The only problem wi th this method is that it is very slow and can not guarantee a global optimal solution.3.2.4 Convex Optimization and geometric Programming MethodsGeometric programming methods are special optimization problems in which the objective and constraint functions are all convex 22-24. Convex optimization technique can solve the problems having a large number of variables and constraints very efficiently 22. The main advantage of this method for which people generally adopt is that the method gives the global solution. Infeasibility is unambiguously detected. Since a lower bound on the achievable performance is given, so the method uses a completely non- heuristic stopping criterion.3.3 Geometric programming and convex optimizationGeometric programming is a special type of optimization technique in which all the objective must be convex. Before applying this technique it has to confirm that whether the given problem is convex optimization problem or not. Convex optimization problem means the problem of minimizing a convex function subject to convex inequality constraints and linear equality constraints. In IC integration convex optimization and geometric programming has become a more efficient computational tool for optimization purpose. This method has an ability to handle thousands of variables and constraints and solve efficiently. The main advantage of convex optimization technique is that it gives the global optimized value and the robust design. The fact that geometric programs can be solved very efficiently has a number of practical consequences. For example, the method can be used to simultaneously optimize the design of a large number of circuits in a single large mixed-mode integrated circuit. The designs of the individual circuits are coupled by constraints on total power and area, and by various parameters that affect the circuit coupling such as input capacitance, output resistance, etc. Convex optimization is used to find out the optimized value of the se parameter and sizing of the devices in the circuit 25. Another application is to use the efficiency to obtain robust designs i.e., designs that are guaranteed to meet a set of specifications over a variety of processes or technology parameter values. This is done by simply replicating the specifications with a (possibly large) number of representative process parameters, which is practical only because geometric programs with thousands of constraints are readily solved. A real valued function fx defined on an interval (space) is called convex ifftx1+1-tx2tfx1+1-tfx2 (11)For every t,0In the Figure 3.1 function fx is represented as a convex function on an interval.The convex optimization problem is in the form of minimize f0xSubjected to fix1 , i=1, 2, 3, mgix=1 , i=1, 2, 3, pxi1 , i=1, 2, 3, nWhere fix is a posynomial functiongix is a monomial functionLet x1,x2xn be n real positive variables. We can denote the vector (xi,xi.xi) of these variables asx. A function f is called a posy nomial function of x if it has the formfix1,x2xn=k=1tCkx11kx22k..xnnk (12)Where Cj0 and ij R. The coefficients Cj must be nonnegative but the exponents ij can be any real numbers including negative or fractional. When there is precisely one nonzero term in the sum i.e. t=1 and C10, we call f is a monomial function.3.3.1 Advantages Handle thousands of variables and constraints and solve efficiently. Global optimization can be obtained.3.3.2 Disadvantages* Strictly limited to types of problems, performance specification and objectives that can be handled.3.4 Optimization of the VCO circuitIn my earlier design of the VCO circuit, the sizes of all the five inverter stages are same. Now the convex optimization technique is applied to find out the optimal scaling ratio of the different inverter stages to get the optimal design with a better performance. There are 5 inverter stages and the design has to give a slow up of 100ps. The load capacitance of the VCO circuit is 65 fF. All these design constraints are explicate and applied to the convex optimization technique. Mainly optimization techniques are applied for selection of component values and transistor sizing.In this work I have used the geometric programming technique to find out the optimized scaling ratio of the different stages in CSVCO to meet the desired center frequency with lesser deviation. Let xi is the scaling ration of the ith stage, CL is the load capacitance, and D is the total delay of the inverter stages then optimization problem is in the form of pick at sum (xi)Subjected to CLCLmaxDDmaxWhere CLmax and Dmax are required design parameters and has a constant value.CHAPTER 4DESIGN AND SYNTHESIS OF PLL4.1 Design EnvironmentThe schematic level design entry of the circuits is carried out in the CADENCE Virtuoso Analog Design Environment. The layout of the PLL is designed in Virtuoso XL using GPDK090 library. In order to analyze the performances, these circuits are simulated in the Spectre simulato r of CADENCE tool. Different performance indices such as phase noise, power consumption and lock time are measured in this environment. Transient, parametric sweep and phase noise analyses are carried out in this work to find out the performances of the circuit. The optimization of the current starved VCO circuit, the scale factor for transistor sizing is found out using the MATLAB environment.4.2 Design Procedure4.2.1 VCO DesignSince VCO is the heart of the whole PLL system, it should be designed in a proper manner. The design go for the current starved VCO are as follows.Step 1 acknowledge the value of the propagation delay for each stage of the inverter in the VCO circuit using the following equation.p=1Nf (13)Where p= phl= plh= half of the propagation delay time of the inverterN= no of inverter stagesf= required center frequency of oscillationStep 2Find the WL ratio for the transistors in the different inverter stages using the equation in below.WL n=CloadphlnCoxVdd-VT,n2VT,nVd d-VT,n+ln4Vdd-VT,nVdd-1 (14)WL p=CloadplhpCoxVdd-VT,p2VT,pVdd-VT,p+ln4Vdd-VT,pVdd-1 (15)Step 3After finding the WL ratio, find the values for W and L.Step 4Find the value of the total capacitance form the fashionCtot=52Cox(LpWp+LnWn) (16)Where Cox is the oxide capacitanceLp,Wp,Ln,Wn is the width and length of the PMOS and NMOS transistors in the inverter stages.Step 5Calculate the value of drain current for the center frequency which is given byIDcenter=NCtotVddf (17)Step 6Find the WL ratio for the current starving transistors in the circuit from the drain current expression which is represented asWL n=2IDcenternCoxVgs-VT,n2 (18)Similarly WL p=2.5WL n (19)4.2.2 Design of Phase Locked LoopThe value of the charge pump current and the component parameters of the loop filter play a major role in the design of the phase locked loop circuit. The value of the lock time mainly depends upon these parameters. So while designing the circuit proper care should be taken in calculating these par ameters. For the given values of reference(Fref) and output frequency(Fout) as well as the lock in range, the following steps to be carried out in designing the filter circuit.Step 1Find the value of the divider circuit to be used which is given byn=FoutFref (20)Step 2Find the value of the natural frequency (n) from the lock in range as given belowlock in range=2n (21)Step 3Find the value of the charge pump gain (KPDI) from the charge pump current used in the circuit which is given byKPDI=Ipump2 (Amps/radian) (22)Step 4Find the value of the gain of the VCO (Kvco) circuit from the characteristics curve using the following expression.Kvco=fmax-fminVmax-Vmin (Hz/V) (23)Step 5Find the values of the loop filter component parameters using the following expressions.C1=KPDIKvcoNn2 (24)C2=C110 (25)R=2nC1 (26)4.3 Design Specifications and Parameters4.3.1 VCO Design SpecificationThe current starved VCO design specifications are mentioned in the following table.Table 1 VCO design specifications 4.3.2 VCO Design ParametersTable 2 List of design parameters of the CSVCO circuit4.3.3 PLL Design ParametersThe whole PLL system design specifications and parameters are shown in the Table 3.ParameterValueReference frequency((Fref)500 MHzoutput frequency(Fout)1 GHzLock in range100 MHz